Spare block cache (SprBlk): Fault resilience and reliability at low voltages
Title
Spare block cache (SprBlk): Fault resilience and reliability at low voltages
Subject
Circuit faults
Computer architecture
Delays
Integrated circuit interconnections
Logic gates
Low voltage
Reliability
Description
This paper proposes a novel cache architecture that uses spare cache blocks to work as back up blocks in a set associative cache, which can operate reliably at voltages well below the manufacturing induced operating voltage (Vccmin). We detect errors in all cache lines at low voltage (i.e. persistent error), tag them as either faulty or fault-free. At runtime, we bypass the faulty words. To bypass faulty words, we use adder and shifter circuitry. Furthermore, we develop a fault model to find the cache set failure probability at low voltage. At 485 mV, SprBlk cache operates with a 16.7% lower bit failure probability compared to a conventional cache operating at 782 mV. Additionally, SprBlk reduce power consumption by 1% when implemented in the L1 data cache only, by 75% when implemented in the L2 cache only, and by 76% when implemented in both caches.
1-4
Creator
N. A. Siddique
A. -H. A. Badawy
Publisher
2017 IEEE SmartWorld, Ubiquitous Intelligence & Computing, Advanced & Trusted Computed, Scalable Computing & Communications, Cloud & Big Data Computing, Internet of People and Smart City Innovation (SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI)
Date
2017
Type
conferencePaper
Collection
Citation
N. A. Siddique and A. -H. A. Badawy, “Spare block cache (SprBlk): Fault resilience and reliability at low voltages,” Lamar University Midstream Center Research, accessed May 14, 2024, https://lumc.omeka.net/items/show/26825.